A memory module, such as a DIMM (Dual Inline Memory Module), constituting a main memory of an information processing apparatus is installed on an information processing apparatus, such as a personal computer. For example, as illustrated in FIG. 10A, an information processing apparatus 500 includes a CPU (Central Processing Unit) 510, a chip set 520, and a DIMM 530.
The CPU 510 is an arithmetic processing device for performing data calculation and processing and is configured to instruct the chip set 520 to write data into the DIMM 530 and to read data out of the DIMM 530. The chip set 520 is a memory control device connected to the DIMM 530 and performs data writing into the DIMM 530 and data reading out of the DIMM 530 based on an instruction given from the CPU 510. The DIMM 530 includes a plurality of DRAMs (Dynamic Random Access Memories) 531a to 531d, whereby various pieces of data are stored in the DRAMs 531a to 531d. 
If a memory error occurs in the DIMM 530, while the information processing apparatus as described above is in operation, the operation of the information processing apparatus may be temporarily stopped to replace the DIMM 530 that has failed with a new DIMM 530, burdening the user of the information processing apparatus. The memory error is induced by generation of a defective block (i.e., a defective area). The memory error prevents data from being stored in affected memory blocks (storage areas) that are installed in the DRAMS 531a to 531d. 
FIG. 11 illustrates an example of a process to be performed when a memory error occurs in a DIMM. As illustrated in FIG. 11, when a power source is turned on, the chip set 520 starts to monitor defect occurring statuses in the DRAMs 531a to 531d (step S501). The chip set 520 determines whether a defect occurrence in any one of the DRAMs 531a to 531d has been detected (step S502). In this process, when an error occurrence in any one of the DRAMs 531a to 531d is not detected (“No” at step S502), the process returns to step S501 and the chip set 520 continues to monitor the defect occurring statuses in the DRAMs 531a to 531d. When the chip set 520 determines that a defect occurrence in any one of the DRAMs 531a to 531d has been detected (“Yes” at step S502), the chip set 520 saves defect information (step S503) and then turns the power source off (step S504) to terminate the process. The DIMM 530, which has been determined to be defective, is replaced with a new DIMM 530.
Respective pieces of defect information of the respective DRAMs 531a to 531d are gathered together and stored in a nonvolatile memory 532 installed in the DIMM 530, as illustrated in FIG. 10A. As an alternative, the defect information of the respective DRAMs 531a to 531d may be discretely stored in nonvolatile memory areas 533a to 533d installed in the respective DRAMs 531a to 531d, as illustrated in FIG. 10B.
As described above, it may be difficult to utilize the DIMM even when there is only one defective block present in the DIMM. A technique of utilizing a redundant area prepared in a DRAM as an alternative area for the defective block has been used to utilize the DIMM having the defective block.
An example of the previously discussed technique is illustrated in FIG. 12. As illustrated in FIG. 12, an information processing apparatus 600 includes a CPU 610, a chip set 620, and a DIMM 630. DRAMs 631a to 631d in the DIMM 630 include redundant areas 632a to 632d, respectively. A nonvolatile memory 633 for storing defect information of the DRAMs 631a to 631d is installed in the DIMM 630. The nonvolatile memory 633 stores defect information about a defective block that has been detected in an electrical test performed before shipment of the information processing apparatus 600.
FIG. 13A illustrates an example of a process performed when a memory error has been detected in an electrical test. As illustrated in FIG. 13A, when the electrical test is started, a process of detecting a defective block included in any one of the DRAMs 631a to 631d is performed (step S601). When the defective block is detected in the process (“Yes” at step S602), defect information is saved (step S603). The defective block, which has been detected by the detecting process performed at step S601, is repaired in hardware, whereby data, whose writing into the defective block has been instructed, is written into a redundant area (step S604). At the completion of this process, or when a defective block has not been detected (“No” at step S602), the electrical test of the DIMM 630 is terminated.
Next, FIG. 13B illustrates an example of a process to be performed when access to a defective block has been instructed while the information processing apparatus is in operation. As illustrated in FIG. 13B, when the power source of the information processing apparatus 600 is turned on, the chip set 620 expands the defect information stored in the nonvolatile memory 633 onto the respective DRAMs 631a to 631d (step S611) and then determines whether access to the defective block has been instructed from the CPU 610 (step S612). When it is determined that access to the defective block has been instructed (“Yes” at step S612), the chip set 620 gains access to the redundant areas 632a to 632d (step S613) instead of gaining access to the defective block. Hence, when data is written into a defective block as instructed from the CPU 610, the chip set 620 operates to write data into the redundant areas 632a to 632d instead of the defective block.
When the process at step S613 is completed or no further instructions have been given from the CPU 610 to access the defective block at step S612 (“No” at step S612), the chip set 620 determines whether the power source has been turned off (step S614). If the power source is not turned off (“No” at step S614), the chip set 620 returns the process to step S612. If the chip set 620 determines that the power source has been turned off (“Yes” at step S614) the process is terminated. As described above, the DIMM 630 may be utilized even if a defective block has been detected in the DIMM 630 during the electrical test by utilizing the redundant areas as alternative areas for the defective block as disclosed in, for example, Japanese Laid-open Patent Publication No. 2004-55100 (JP-A-2004-55100).
However, in JP-A-2004-55100, a process of putting data into a redundant area instead of a defective area is performed only when defect information is stored when a CPU is electrically tested. Thus, although a defective block may be detected to be present upon shipment, it may be possible to put data, whose writing into the defective block has been instructed, into another area as a refuge, or alternative area. Whereas, for a defective block that has been freshly generated while the information processing apparatus is in operation, it may be difficult to put the data into another area as an alternative area.
In JP-A-2004-55100, an alternative area for the defective block for writing data is limited to the redundant area. Hence, when the capacity of the redundant area is used up, the redundant area may not be used any more as an alternative to the defective block.
In addition, in JP-A-2004-55100, when a defective block is detected during the electrical test, the defective block is repaired in hardware, whereby data, whose writing into the defective block has been instructed, is written into redundant areas. Once the defective block is repaired in hardware, it may be difficult to bring the defective block back to its original state, and thus it becomes difficult to seek out a defective block improving process and to examine fundamental causes for the generation of defective blocks. Thus, for example, a DIMM, in which many defective blocks have been detected, may be discarded with no examination of the fundamental causes for the generation of the defective blocks, and no process for eliminating the occurrence of defective blocks may be performed, thereby reducing the production yield of usable DIMMs.